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Backend-Terminated (BUSY) Cycle during Data Burst (Target)
If the backend runs out of data during a burst transfer (a FIFO empties), the backend can terminate the transfer by
asserting BUSY. The core will then terminate the PCI cycle with a disconnect with or without data, depending on the
state of the internal data pipe. The core will delay asserting the PCI STOPN signal until the internal FIFO is empty. It
is recommended that the RD_STB_IN signal be deasserted once BUSY is asserted. Otherwise, the core will continue to
accept data from the backend and transfer it on the PCI bus.
If the backend does not assert the RD_STB_IN or WR_BE_RDY signals within the eight-clock-cycle requirement, the
PCI core will automatically terminate the PCI cycle.
cycle
0
1
2
3
4
5
6
7
8
9
clk
framen
ad[31:0]
cben[3:0]
ADDR
6
0
0
1
par
devseln
irdyn
trdyn
stopn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
busy
error
0
mem_add[11:0]
mem_data_in[31:0]
000
0
004
1
rd_sync
Figure 6-27 · Backend Burst Read Cycle Terminated by BUSY (RD_SYNC = 0)
Once asserted, BUSY may be deasserted, as in Figure 6-27 , or left asserted until the backend has data available. This
would cause any subsequent PCI cycles to be terminated with a retry.
76
v4.0
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